The invention relates to a converter circuit for converting a DC input voltage to an AC output voltage. In particular, the invention relates to a half-bridge inverter for converting a DC input voltage to provide an AC output voltage at the output terminal thereof.
These days, there exists a high demand for highly efficient power converters, for instance, for use as solar inverters, in power generators, or as power converters for high speed motor drives or for uninterruptible power supplies. At the same time, it is more and more important to reduce the costs of said power converters by replacing circuits based on the SiC MOS-FET or JFET technology with a standard silicon BJT/MOS-FET/IGBT technology applied to high power applications.
Generally, there are several techniques known in the prior art to improve the overall power efficiency of a power converter employing MOS-FET/IGBT switching elements.
In particular, a highly efficient power converter with MOS-FET/IGBT switching elements is described in “Advantages of NPC Inverter Topologies with Power Modules” by Temesi, Ernö and Frisch, Michael, Power Electronics Europe, Sep. 4, 2009. In particular, this document describes different power converter circuits, some based on a NPC inverter topology, others based on a half-bridge topology. In particular, a proposed half-bridge inverter is shown in FIG. 4.
The half-bridge inverter, as illustrated in FIG. 4, includes a half-bridge switching stage connected to the DC+ and to the DC− input terminals. By enabling the upper IGBT of the half-bridge switching stage, a positive voltage can be provided at the output terminal OUT. By enabling the lower IGBT of the half-bridge switching stage, a negative voltage can be provided at the output terminal OUT.
In a transition period in between the enabling of the upper and of the lower IGBT, the output terminal may be provided with a neutral potential from the neutral terminal, for instance with ground connection. The connection to the neutral terminal is provided via two IGBTs and two diodes.
Due to the design of the half-bridge switching stage a single IGBT transistor is connecting an input terminal to the output terminal. Accordingly, the conductive losses of the design are small in comparison with an NPC inverter comprising a switching stage with four transistors. However, a single transistor connecting the input and the output terminal requires a higher voltage rating specifying the transistor's voltage blocking capabilities in a non-conducting state. Accordingly, the high voltage rating results in limitations on the switching performance.
For improving the switching performance, it is known to provide a parallel circuit of an IGBT and of a MOS-FET. In particular, a parallel circuit of an IGBT and of a MOS-FET can be configured to assign the static losses to the IGBT and the switching losses to the MOS-FET. Further, a fast switching speed of a MOS-FET is advantageous for reducing the switching losses. Thus, the MOS-FET may be set to carry the current during a low power period or a transition period and the IGBT may be set to carry the majority of the load in a high power period in order to improve the overall efficiency.
Accordingly, the parallel circuit of an IGBT and a MOS-FET may help improving the switching performance of the described half-bridge switching stage. However, the parallel circuit would also be limited to the same high voltage rating as the half-bridge shown in FIG. 4; wherein the necessary high voltage rating introduces a negative effect on the switching performance of MOS-FET as well as the IGBT.
In summary, the known techniques for improving the efficiency of power converters do not meet the requirements of a highly efficient half-bridge inverter in a satisfying manner.